The Qualcomm Data Center team is developing high-performance, energy-efficient server solutions for data center applications. We are looking for highly talented, innovative, and collaborative individuals to join our advanced platform engineering work. 

Our Mission 

We are dedicated to transforming the industry by reimagining silicon and developing next-generation computing platforms. You will collaborate with world-class engineers to create solutions that advance performance, energy efficiency, and scalability. Our focus is on Qualcomm data center reference platforms that bring together hardware, software, reference designs, user guides, SDKs, and related enablement collateral. 

Position Summary 

We are seeking a senior Signal Integrity Architect to own PCIe Gen 6+ and CXL signal integrity across Qualcomm data center server platforms. The role is the primary SI owner for the PCIe-based interconnect domain, including REFCLK and retimer/redriver integration, and is accountable for end-to-end channel analysis, design closure, interface-specific methodology, and validation planning. You will collaborate closely with platform, silicon, package, board, firmware, validation, and component engineering teams to deliver robust system-level designs. 

Key Responsibilities 

• Own end-to-end SI analysis and design closure for PCIe Gen 6+ and CXL interfaces from early architecture through platform validation. 

• Develop channel budgets, margin analyses, design rules, signoff criteria, and correlation plans for PCIe/CXL links. 

• Own SI architecture and technical guidance for PCIe REFCLK distribution, including jitter-budget and topology considerations. 

• Own SI analysis and integration guidance for retimers and redrivers, including placement, channel partitioning, model use, and system margin. 

• Build and maintain package-to-board and full-channel simulation models using frequency-domain and time-domain methods, including S-parameter and IBIS-AMI based analysis as applicable. 

• Provide actionable guidance for PCB stackups, materials, routing constraints, via transitions, connectors, cables, and component selection within the PCIe/CXL domain. 

• Assess die/package SI inputs and package-to-board interactions for PCIe/CXL, working with silicon and package teams and providing recommendations to the SI Lead for platform integration and signoff. 

• Define PCIe/CXL validation and platform-compliance-evidence methodology; partner with the validation engineer on measurement execution, lab correlation, margin demonstration, and debug. 

• Partner with firmware, system, and component teams on link bring-up, equalization, retimer firmware interactions, interoperability, and root-cause analysis. 

• Develop and automate analysis flows to improve productivity, accuracy, repeatability, and scalability. 

• Contribute interface-specific content to design guides, customer collateral, technical reviews, and recommendations for engineering teams, senior leadership, customers, suppliers, and ODM partners. 

• Mentor engineers and provide technical direction within the PCIe/CXL area of ownership. 

Qualifications 

• Masters degree in Electrical Engineering, Computer Engineering, or a related field. 

• 10+ years of experience in signal integrity analysis, simulation, and validation of high-speed digital systems. 

• Demonstrated ownership of PCIe interface SI from architecture and specification through system validation; PCIe Gen 6 or comparable high-speed SerDes experience strongly preferred. 

• Strong knowledge of transmission-line theory, channel analysis, insertion and return loss, crosstalk, S-parameters, jitter, equalization, link margin, and system-level optimization. 

• Experience with PCIe/CXL channel modeling, compliance methodology, REFCLK analysis, and retimer/redriver integration. 

• Hands-on experience creating package-to-board and full-channel models and performing frequency-domain and time-domain simulations. 

• Proficiency with one or more relevant simulation environments, such as ANSYS HFSS/SIwave, Cadence Sigrity/Clarity, Dassault Systemes CST, Keysight ADS, or Synopsys HSPICE. 

• Experience with electrical validation and correlation using oscilloscopes, VNAs, TDR systems, BERTs, protocol analyzers, traffic generators, or related laboratory equipment. 

• Proficiency in Unix/Linux environments and scripting for EDA workflow automation. 

• Strong understanding of package and PCB technologies, design methodology, and manufacturing processes. 

• Demonstrated ability to independently drive complex cross-functional SI projects with limited supervision. 

• Strong written, verbal, and presentation skills. 

Preferred Qualifications 

• Ph.D. in Electrical Engineering, Computer Engineering, or a related field. 

• 15+ years of experience in SI analysis, simulation, validation, and architecture of high-speed systems. 

• Deep hands-on experience with PCIe Gen 6+ channel modeling, link simulation, compliance verification, lab correlation, and debug on server-class platforms. 

• Practical knowledge of CXL physical-layer implementation and interoperability considerations. 

• In-depth understanding of computational electromagnetics, equalization techniques, PAM4 signaling, and SerDes link analysis. 

• Experience qualifying vendor or internally generated channel models, including IBIS-AMI and S-parameter models. 

• Experience with package and PCB design tools such as Cadence Allegro. 

• Proficiency in Python, MATLAB, Perl, or comparable scripting and automation environments. 

• Experience developing server, AI, HPC, data center, or other high-performance computing platforms.