Sr. Engineer, Performance Infrastructure

Location: Austin, Texas, United States; Santa Clara, California, United States

Department: RISC V

We are looking for a talented engineer to join our CPU design team to drive infrastructure for performance analysis, correlation and verification. You’ll work on a CPU based on RISC-V ISA, collaborating with core architects and RTL teams to deliver a highly efficient and performant design.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

 

Who You Are

• Strong problem solver who can identify complex issues, develop practical solutions, and drive them through implementation.
• Enjoy building tools and improving the infrastructure, workflows, and methodologies that make CPU development more efficient.
• Skilled in C++ and Python, with experience using industry-standard compilation, simulation, and emulation tools.
• Experience with verification infrastructure and methodologies along with knowledge of high-performance CPU architecture and microarchitecture.
• Proficient in debugging RTL and logic across multiple design hierarchies and pre-silicon environments.

 

What We Need

• Join a team driving improvements in CPU microarchitecture, verifying performance, and correlating results between RTL and the performance model.
• Enhance the design environment, tools, and methodologies to improve development efficiency.
• Own the performance correlation framework, including tracking, visualization, and analysis tools.
• Collaborate closely with RTL engineers and core architects to meet performance goals, debug miscorrelation, and verify performance features.
• Use innovative techniques to optimize power, performance, and area while driving performance experiments and evaluating results.

 

What You Will Learn

• End-to-end exposure to CPU design from microarchitecture through performance convergence and validation.
• Hands-on experience with performance models, correlation, and analysis across pre-silicon and post-silicon phases.
• Experience integrating open-source and industry-standard tools to improve design flows and results.
• How to work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.