Our Mission

We are dedicated to transforming the industry by reimagining silicon and developing next-generation computing platforms. By joining our team, youll collaborate with world-class engineers to create innovative solutions that push the limits of performance, energy efficiency, and scalability. Our focus is on developing reference platforms based on Qualcomms Snapdragon SoC, delivering a comprehensive solution that includes hardware, software, reference designs, user guides, SDKs, and more.

About the Role

As a Staff / Sr. Staff System FPGA Engineer (individual contributor), you will work closely with the platform team and collaborate with cross-functional teams, including SoC, software, firmware, hardware, and component suppliers. You will be responsible for implementing defined FPGA architectures for control-plane and telemetry systems on next-generation server reference platforms. You will contribute hands-on across RTL development, simulation, verification, testing, and lab bring-up, while proactively identifying and escalating architectural concerns when implementation reveals issues that need to be addressed.

Key Responsibilities

• Implement RTL designs based on defined system architectures, translating specifications into synthesizable HDL.

• Develop and execute test benches and verification plans for FPGA designs using industry-standard tools and frameworks.

• Perform FPGA synthesis, place-and-route, and timing closure using vendor toolchains.

• Test and debug FPGA designs in the lab using hardware bring-up tools, JTAG, logic analyzers, and oscilloscopes.

• Identify implementation-level issues and provide clear, constructive feedback to architects and senior engineers when design specifications require clarification or correction.

• Develop Python-based scripts and cocotb test benches to support design automation, regression testing, and verification infrastructure.

• Maintain and contribute to source-controlled design repositories using git and GitHub, following team branching and review workflows.

• Participate actively in peer code reviews, maintaining high standards for RTL quality, readability, and maintainability.

• Produce clear technical documentation covering implementation details, test results, and known issues.

• Collaborate with hardware, firmware, and software teams during system bring-up and integration phases.

• Engage with suppliers, customers, and multi-site team members as needed, with some travel expected to support these activities.

Qualifications

• Bachelors or Masters degree in Computer Science/Engineering, Electrical Engineering, or a related field.

• 5+ years of experience in FPGA implementation and verification.

• Strong understanding of logic design and standard industry interfaces.

• Experience in FPGA design optimization.

• Proven experience with common interfaces such as I2C, UART, AXI4, PCIe, DDR5, or similar protocols.

• Proficiency in HDL development — Verilog and/or SystemVerilog — including simulation, test bench creation, synthesis, and debugging using CAD tools.

• Proficiency in Python scripting for design automation, test infrastructure, and tooling.

• Working knowledge of git and GitHub for version control, collaborative development, and CI/CD workflows.

• Experience with cocotb for Python-based RTL verification.

• Hands-on experience with FPGA development tools and hardware bring-up.

• Strong written and verbal communication skills, including the ability to document findings and flag issues clearly.

Preferred Qualifications

• Masters degree in Computer Science/Engineering, Electrical Engineering, or a related field.

• 10+ years of hands-on experience in FPGA implementation, verification, and system integration.

• Demonstrated experience implementing complex control-plane or telemetry functions on FPGA platforms within a defined architectural framework.

• Advanced proficiency with high-speed interfaces including SerDes, PCIe 5/6, DDR5, LPDDR5X, or similar.

• Experience with embedded soft-core processor integration (e.g., MicroBlaze, NIOS II, or RISC-V).

• Familiarity with vendor-specific toolchains such as AMD/Xilinx Vivado/Vitis or Intel/Altera Quartus Prime.

• Experience authoring timing constraints (XDC/SDC) and performing timing closure on complex multi-clock designs.

• Knowledge of Clock Domain Crossing (CDC) techniques and formal CDC analysis methodologies.

• Familiarity with SystemVerilog Assertions (SVA) and functional coverage methodologies.

• Experience with CI-driven simulation and regression flows integrated with git-based repositories.

• Background in server management standards such as IPMI, MCTP, PLDM, or OpenBMC ecosystems.

• Demonstrated AI-first engineering mindset — comfortable leveraging AI-assisted tools and workflows (e.g., code generation, automated documentation, intelligent debugging) to meaningfully enhance personal and team productivity.