Digital Verification Engineer

Location: South San Francisco, California, United States

Department: Brain Interfaces Hardware

Job Description & Responsibilities: 

We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification fundamentals to work in Neuralink’s System-on-Chip (SoC) department under the Implant Team. This position offers a rare and unique opportunity to have a high impact in realizing state-of-the-art brain-computer interfaces. The team delivers architecture and logic implementation of digital modules with a strong focus in high-throughput low-power digital signal processing (DSP) . We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Key qualifications:

• Minimum 3 years of experience in digital ASIC verification.
• Excellence in SystemVerilog.
• Experience in developing automation flow and scripts such as Python, Perl, Makefile, Tcl and UNIX shell
• Experience with code coverage and regression setup.

Preferred qualifications:

• Experience working on complex digital systems from architecture, microarchitecture, RTL, verification and physical design using industry standard tools.
• Experience on building test benches, testing, and debugging for a complex system-on-chip.
• Experience in formal verification.
• Functional modeling experience and logic verification with SystemVerilog, SystemC/C++.
• Experience with IEEE-1801 (UPF) based design simulation flows
• Experience with low power gate level simulations
• Exposure with low power formal verification flows
• Strong hands-on experience in verification methodologies such as UVM
• Knowledge of ARM/RISC-V processor, AMBA bus
• Knowledge of power aware verification
• Experience with FPGA/emulation
• Experience with lab system bring up, writing diagnostic, and lab debugging