CPU Core Physical Design Engineer

Location: US, California, Folsom

Time Type: Full time

Job Description

Job Details:

Job Description: 

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, youll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone


Were looking for motivated and talented engineer to join the US CPU design team. In this role you will be critical to the development of next generation CPUs designed to power the AI revolution.



The CPU Physical Design Engineer:

• Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
• Possesses CPU-specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
• Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, lowpower synthesizable CPU.
• Optimizes CPU design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Highly qualified candidates will possess the following Behavioral traits:

• Strong problem solving.
• Tolerance of ambiguity.

Business Group
You will join the Data Center Group (DCG), a global leader in developing cutting-edge technologies that power the infrastructure of the digital economy. This team is at the forefront of enabling advancements in cloud computing, artificial intelligence, and data analytics, delivering world-class solutions that support Intels broader mission of creating world-changing technology. DCG fosters collaboration across diverse disciplines to design and optimize CPUs that meet the demands of todays data-driven world.

Key Responsibilities
- Implement physical design flows for custom CPU designs, transitioning from RTL code to GDS format.
- Conduct synthesis, place and route, clock tree synthesis, and floor planning processes.
- Perform static timing analysis, reliability verification, and power distribution optimization.
- Execute verification and signoff processes, including formal equivalence, electrical rule checking, and layout validation.
- Partner with cross-functional teams, including logic, circuit, architecture, and design automation experts, to optimize CPU microarchitectures.
- Collaborate with EDA vendors to enhance tool capabilities that support the design of high-speed, low-power CPUs.
- Develop and refine methodologies and automation flows to improve design processes and efficiency.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.


Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

• The candidate must possess a bachelors degree in computer engineering, Computer Science or Electrical/Electronic Engineering or any STEM related degree and 1+ years of experience OR masters degree in computer engineering, Computer Science or Electrical/Electronic Engineering or any STEM related degree.
• 3+ months of experience in VLSI circuit design and synthesis.
• 3+ months of experience in Static timing analysis
• 3+ months of experience in Low power design

Preferred Qualifications:
Experience in:

• x86 CPU architecture.
• Tcl/Perl/Python programming.

Benefits at Intel

Our total rewards package goes above and beyond just a paycheck. Whether youre looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.

Job Type:

College Grad

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, Folsom

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

 

 

Annual Salary Range for jobs which could be performed in the US: $105,650.00-172,860.00 USD

 

 

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

 

 

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.