Senior Physical Design Engineer - P&R

Location: Remote

• Run place and route implementation flows and analyze the results.
• Create effective floorplans that support physically aware synthesis.
• Drive designs to timing closure and run physical verification.
• Debug issues spanning tools, timing constraints, DFT, and design.
• Partner with the design team to improve RTL and make it implementation friendly.
• Implement and apply timing ECOs.
• Run PrimeTime and analyze timing reports.
• Develop strategies to optimize power and area.
• Run IR-drop analysis and identify optimal strategies to improve it.
• Interface with analog and front-end teams to align on shared objectives.

• 8 or more years of relevant experience in ASIC digital place and route.
• Recent, hands-on experience with leading EDA tools and advanced flows (Synopsys and Cadence).
• Strong understanding of advanced FinFET technology nodes, DRC rules, and node-specific P&R requirements.
• Practical experience with floorplanning.
• Solid grasp of CTS concepts and the ability to design clocks to meet timing requirements.
• Working knowledge of IR-drop optimization strategies.
• Experience with timing closure and ECO implementation (PT-ECO or Tweaker experience is an asset).
• Strong scripting skills.
• Exposure to several of the following: synthesis, StarRC, PT DMSA, RedHawk, Calibre, and formal verification (LEC or Formality).
• A track record as a self-starter who also works well within a team.