The Opportunity

ADI is seeking a talented and experienced Staff Design Verification Engineer to help develop next-generation eFPGA technology and the SoCs that integrate it. This role is ideal for engineers with strong digital design verification expertise, including UVM-based methodologies, SystemVerilog assertions, and end-to-end silicon verification.

While prior eFPGA experience is not required, candidates should possess a solid background in digital hardware design, architecture, and verification. You will work closely with cross-functional engineering teams to verify complex subsystems and ensure the successful delivery of high-quality silicon products.

What Youll Do

• Partner with architecture, RTL, firmware, and software teams to understand new features and define comprehensive verification strategies.

• Develop detailed verification plans covering feature interactions, system-level behavior, and hardware/software use cases.

• Design, implement, and maintain directed and constrained-random verification environments and test suites.

• Develop SystemVerilog assertions and functional coverage models to ensure thorough verification.

• Debug simulation failures, identify root causes, and collaborate with design and firmware engineers to resolve issues.

• Analyze functional and code coverage metrics and enhance verification content to achieve coverage goals.

• Build and support end-to-end verification flows for eFPGA soft logic within SoCs, including RTL simulation, synthesis validation, and bitstream generation.

• Contribute to verification methodology improvements, automation, and continuous integration workflows.

Minimum Qualifications

• Masters degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent industry experience.

• Strong understanding of SoC architectures and industry-standard bus protocols such as AXI and AHB.

• Experience debugging RTL and firmware using simulation and waveform analysis tools.

• Hands-on experience developing UVM-based verification environments.

• Proficiency in SystemVerilog, Verilog, C/C++, and Python.

• Experience developing automation solutions and working within distributed compute environments.

• Working knowledge of SystemC and Transaction-Level Modeling (TLM).

• Strong communication and collaboration skills, with the ability to work effectively across multidisciplinary teams.

• Solid understanding of digital design fundamentals, computer architecture, timing analysis, power analysis, process variation, and reliability considerations.

Preferred Qualifications

• 5+ years of experience in SoC, subsystem, or microarchitecture verification.

• Experience supporting successful silicon tape-outs in advanced process nodes (N4, N5, or similar technologies).

• Knowledge of Functional Safety (FuSA) requirements and safety-focused hardware verification methodologies.

• Experience with FPGA or programmable logic architectures.

• Familiarity with continuous integration, regression automation, and verification productivity tools.

About the Team

ADIs Embedded FPGA (eFPGA) team plays a key role in enabling product differentiation across our platform SoCs. The team drives innovation in heterogeneous processing, hardware adaptability, and high-performance edge computing solutions across a wide range of markets and applications.

Through architectural innovation and execution across multiple complex programs, the eFPGA team continues to advance programmable hardware as a core element of ADIs Intelligent Edge strategy. Our technology enables high-speed, real-time processing while providing customers with the flexibility to adapt hardware functionality to evolving system requirements.