<div>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</div>We are seeking an experienced IP Packaging and Methodology Engineer to join our RISC-V IP Engineering team. This role is critical to establishing and scaling our IP delivery infrastructure as we expand our portfolio of CPU cores, memory controllers, and peripheral IP blocks for both internal consumption and external licensing. Youll architect automated packaging workflows, establish quality gates, and drive cross-functional process improvements that enable reliable, high-quality IP delivery. Think of this role as SRE for Hardware IP or The Infra Team for Silicon. This role is hybrid, based out of Santa Clara, CA or Austin, TX, with remote options for exceptional candidates in other (US) locations. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.   Who You Are <ul> <li>5+ years in semiconductor IP development, ASIC/SoC design, or related hardware engineering disciplines with BS/MS in Computer Engineering, Electrical Engineering, or Computer Science.</li> <li>Expert-level Python and Bash scripting for automation and tooling development, with advanced Git/GitLab proficiency including CI/CD pipelines.</li> <li>Proficient in SystemVerilog/Verilog with ability to review and debug RTL implementations across complex design hierarchies.</li> <li>Deep understanding of CPU microarchitecture (pipeline design, cache hierarchies, memory subsystems) and industry-standard interconnect protocols (AMBA AXI/AHB/APB, TileLink, Wishbone).</li> <li>Experience with EDA tools: simulators (VCS, Xcelium, Verilator), lint tools (SpyGlass Lint), physical design tools (Formality, Design Compiler).</li> <li>AI-enhanced productivity: Leveraging LLM tools (Cursor, GitHub Copilot, ChatGPT, Claude) to accelerate development, debugging, and documentation—youre 10x-ing yourself with AI.</li> <li>Systems thinker who automates reflexively and sees how git hooks connect to release quality connects to customer satisfaction.</li> </ul>   What We Need <ul> <li>Design and implement automated IP packaging pipelines using Python, Bash, and GitLab CI/CD frameworks supporting IEEE 1735 encryption, IP-XACT, and ARM AMBA specifications.</li> <li>Establish automated validation gates: lint checking, simulation regression hooks, documentation completeness verification, and generate customer-facing deliverables (datasheets, integration guides, reference testbenches).</li> <li>Analyze and architect scalable solutions for IP delivery workflows, defining best practices for documentation, configuration management, and quality assurance.</li> <li>Debug complex IP integration issues spanning RTL implementation, configuration management, timing constraints, and system-level integration; work within SystemVerilog verification environments.</li> <li>Drive cross-functional initiatives partnering with Design, Verification, Physical Design, Software, and Product Management to standardize IP interfaces and packaging requirements.</li> <li>Lead strategic methodology improvements including infrastructure-as-code and continuous integration strategies that benefit 100+ hardware engineers.</li> </ul>   What You Will Learn <ul> <li>End-to-end IP delivery infrastructure at scale, from design collateral to production-ready licensable assets used by grad students and billion-dollar semiconductor companies alike.</li> <li>DevOps for hardware: Build containerized workflows (Docker/Kubernetes), infrastructure-as-code (Terraform/Ansible), and CI/CD systems specifically designed for semiconductor IP.</li> <li>RISC-V ecosystem expertise working with open-source projects (Chipyard, Rocket Chip, BOOM, CVA6) and understanding how RISC-V is democratizing processor design.</li> <li>Strategic impact: Your automation frameworks will directly influence time-to-market for RISC-V products across automotive, datacenter, IoT, and AI accelerator domains in a competitive marketplace where ARM, Synopsys, and Cadence are watching closely.</li> <li>Thought leadership opportunities through conference presentations, technical publications, and mentoring engineers on IP packaging best practices.</li> </ul>   Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.<div>This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.</div>