<div><p>Waymo is an autonomous driving technology company with the mission to be the worlds most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The Worlds Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo’s fully autonomous ride-hail service and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states.</p></div><p><span>Waymos Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle’s software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world’s highest performance automotive compute platforms. </span></p> <p><strong>You will:</strong></p> <ul> <li>Contribute to all aspects of DFT from methodology, scripting, test insertion, SDC constraints, ATPG generation, and pattern delivery in both a lead and hands-on role</li> <li>Drive ASIC partners &amp; internal  design teams to meet automotive test targets while minimizing the impact on Power, Performance, and Area (PPA)</li> <li>Architect and define hierarchical test strategy and SoC test interfaces</li> <li>Collaborate with architects, designers, functional safety engineers, manufacturing quality, and other partner teams to optimize for a broad range of constraints</li> </ul> <p><strong>You have:</strong></p> <ul> <li>10+ years of experience on DFT/ATPG/Silicon Test in advanced silicon nodes with a minimum of 2 tapeouts</li> <li>Experience owning full chip DFT architecture. Be able to write a DFT architecture spec and work with an ASIC vendor on implementation.</li> <li>Expertise with Scan Based test including compression/decompression, MBIST, LBIST, ATPG, boundary scan, System-Level Test (SLT), and both wafer and package test</li> <li>Experience setting and implementing test methodologies/flows with both internal and external partners including demonstrated scripting ability (Python/TCL)</li> <li>Experience delivering PPA optimal test methodologies that have minimal impact on Physical Design Closure</li> </ul> <p><strong>We prefer:</strong></p> <ul> <li>Experience with automotive silicon, including optimization for low DPPM and FIT rates</li> <li>Experience with functional safety and in-field test</li> <li>Experience with Automotive Qualification (AEC-Q100) standards</li> <li>Understanding of RTL-to-GDS flows, especially as they pertain to test</li> <li>Experience growing a DFT/ATPG team and working with external vendors or partner teams</li> </ul> <p><strong>Travel:</strong></p> <ul> <li>Up to 15% Travel</li> </ul><div><div><div><p><span>The expected base salary range for this full-time position across US locations is listed below. Actual starting pay will be based on job-related factors, including exact work location, experience, relevant training and education, and skill level. Your recruiter can share more about the specific salary range for the role location or, if the role can be performed remote, the specific salary range for your preferred location, during the hiring process. </span></p> <p><span>Waymo employees are also eligible to participate in Waymo’s discretionary annual bonus program, equity incentive plan, and generous Company benefits program, subject to eligibility requirements. </span></p></div><div>Salary Range</div><div><span>$238,000</span><span>—</span><span>$302,000 USD</span></div></div></div>