<div><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p>Tenstorrent is seeking an experienced DFT/DFD Design Verification Engineer for a contract position to support the validation of cutting-edge test architectures in high-performance SoCs. In this role, you will verify Design-for-Test (DFT) and Design-for-Debug (DFD) logic—including JTAG, iJTAG, and internal scan architectures—ensuring robust manufacturability and post-silicon debuggability. You will work closely with DFT architects, RTL designers, and DV teams to develop and execute comprehensive verification plans using industry-standard tools and methodologies.</p> <p>This is a fixed-term contract role and the candidates can be based in the US or Canada, and we are open to remote work.</p> <h3> </h3> <h4><strong>Key Responsibilities:</strong></h4> <ul> <li>Define and execute verification plans for DFT/DFD features such as boundary scan, scan chains, and debug logic.</li> <li>Develop UVM-based or directed tests to validate IEEE 1149.x (JTAG), 1500 (iJTAG), and 1687 (IJTAG) compliant implementations.</li> <li>Verify integration and functionality of ICL (Instrument Connectivity Language) and PDL (Procedure Description Language) content for instrument and test control.</li> <li>Simulate and debug DFT/DFD RTL and gate-level designs using industry-standard simulators.</li> <li>Collaborate with DFT architecture and implementation teams to ensure functional correctness, performance, and alignment with manufacturability goals.</li> <li>Drive coverage closure, including code coverage and functional coverage, across all DFT/DFD blocks.</li> <li>Work with post-silicon validation and ATE teams to ensure test vector portability and alignment between simulation and silicon.</li> </ul> <h3> </h3> <h4><strong>Experience &amp; Qualifications:</strong></h4> <ul> <li>Bachelors or Master’s degree in Electrical Engineering, Computer Engineering, or related field.</li> <li>Proven experience in design verification for DFT/DFD architectures in complex SoC environments.</li> <li>Hands-on experience with IEEE JTAG-related standards: <strong>1149.1</strong>, <strong>1500</strong>, and <strong>1687</strong>.</li> <li>Proficiency in writing and debugging <strong>ICL</strong> and <strong>PDL</strong> files for test generation and instrumentation control.</li> <li>Experience using <strong>Siemens Tessent</strong> tool suite for scan insertion, ATPG, IJTAG, and pattern generation.</li> <li>Solid understanding of RTL verification flows and simulation methodologies.</li> <li>Proficiency in Verilog/SystemVerilog and scripting (Python, Perl, TCL).</li> <li>Strong analytical and debugging skills with attention to detail and documentation.</li> <li>Experience with UVM-based testbench environments for DFT/DFD verification. (preferred)</li> <li>Familiarity with scan compression, LBIST/MBIST, and test access architectures. (preferred)</li> <li>Exposure to gate-level simulations and post-silicon test bring-up workflows. (preferred)</li> <li>Strong collaboration skills with ability to work across architecture, design, and ATE teams. (preferred)</li> <li>Knowledge of scan diagnosis and failure analysis workflows is a plus. (preferred)</li> </ul> <p> </p> <p><em>Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.</em></p> <p><em>Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.</em></p><div><p><em>This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.</em></p></div>