<p>NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice and join us today!<br /> </p><p>This is a dynamic team working with state of the art, unique technology. If you are someone that loves a challenge, come join this diverse team and help move the needle! We are looking for a senior engineer to be part of the mixed-signal design team building next generation NVLINK. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.</p><p></p><p><b>What youll be doing:</b></p><ul><li><p>Develop and implement high speed interfaces and analog circuits. You will have hands on experience taking innovative integrated circuit designs at data rates of 25Gbps and higher from concept through silicon characterization.</p></li><li><p>Help by defining circuit requirements and complete design from schematic, layout, and verification to characterization.</p></li><li><p>Conduct schematic design of deep-submicron CMOS technologies using Spectre, Hspice or like.</p></li><li><p>Take ownership for the architecture, transistor design and verification using industry standard EDA tools such as Cadence virtuoso.</p></li><li><p>Optimize circuit to meet the specifications for system performance.</p></li><li><p>Work closely with layout engineers by providing detailed floorplan and guidance for matching and high-speed routings.</p></li><li><p>Provide support for post-silicon bring-up and debugging.</p></li></ul><p></p><p><b>What we need to see:</b></p><ul><li><p>Hold a Master of Science in Electrical Engineering, Computer Engineering or related field with strong analog design background (or equivalent experience)</p></li><li><p>Minimum of 5 years analog design experience in industry</p></li><li><p>CMOS Analog / Mixed Signal Circuit Design Experience in deep sub-micron process (especially in FINFET)</p></li><li><p>Experience with design and verification tools (Cadences IC design environment, analog circuit simulation tools like Spectre, HSpice, Finesim, XA)</p></li><li><p>Experience in crafting test bench environments for component and top level circuit verification</p></li><li><p>Behavioral modeling of analog and digital circuits</p></li><li><p>Strong debugging and analytical skills</p></li><li><p>Analog simulation for noise analysis, loop stability analysis, ac/dc/tran analysis, monte-carlo, etc.</p></li><li><p>Strong interpersonal skills and ability &amp; desire to work as a great teammate are huge plus.</p></li></ul><p></p><p></p>Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.<div><div><div><div><div><div><div><p></p><p><span>You will also be eligible for equity and <a href="https://www.nvidia.com/en-us/benefits/" target="_blank">benefits</a>.</span></p><p></p></div></div></div></div></div></div></div>Applications for this job will be accepted at least until July 29, 2025.<p></p><p></p>NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.<p></p><p></p>