<p>Do you have a passion for computer gaming, virtual reality, computer vision, and artificial intelligence? Ever dream about inventing your own holodeck? Do you want to work on groundbreaking problems alongside some of the most forward-thinking people in the world?</p><p></p><p>NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.</p><p></p><p><b>What you will be doing:</b></p><ul><li><p>Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with emphasis on PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes</p></li><li><p>Develop flows for advanced place and route methods, floorplanning and chip assembly, power and clock distribution, power and area optimization, timing, IR and EM analysis and closure</p></li><li><p>Work with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all our product lines</p></li></ul><p></p><p><b>What we need to see:</b></p><ul><li><p>Pursuing a MS in Electrical or Computer Engineering (or equivalent experience)</p></li><li><p>Understanding of physical design optimization and routing methodologies at place, cts, route and postroute, especially power and area efficient setup and hold optimization</p></li><li><p>Experience in advanced Clock tree synthesis methods and techniques</p></li><li><p>Strong background in STA, extraction, timing and RC correlation</p></li><li><p>Background with design rules in advanced nodes and their impact on DRC closure and PPA optimization</p></li><li><p>Understanding of power intent files such as UPF, and use of FSDB/SAIFs for power optimization</p></li><li><p>Understanding of hierarchical design, pinning and budgeting flows</p></li><li><p>Experience with power distribution networks, Design for Yield and Manufacturability, EM and IR closure and thermal management</p></li><li><p>Proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++.</p></li></ul><p></p><h2><b>Ways to stand out from the crowd:</b></h2><ul><li><p>Understanding of AI/ML methods in physical design optimization is preferred</p></li><li><p>Knowledge of industry standard EDA tools, <span>with proficiency in Innovus based flows preferred </span></p></li></ul><p></p><p>NVIDIA is widely considered to be one of the technology world’s most desirable employers. And due to outstanding growth, our teams are rapidly growing. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology? If so, we want to hear from you!</p><p></p><p></p>Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD.<div><div><div><div><div><div><div><p></p><p><span>You will also be eligible for equity and <a href="https://www.nvidia.com/en-us/benefits/" target="_blank">benefits</a>.</span></p><p></p></div></div></div></div></div></div></div>Applications for this job will be accepted at least until September 27, 2025.<p></p><p></p>NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.<p></p><p></p>