<div>Mobileye EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving.</div><div>Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution &amp; responsibility . </div><div>Each Physical Design engineer has an E2E responsibility from definition, execution &amp; full signoffs,  working closely with design &amp; architecture teams for constraints development, design review &amp; RTL modifications to achieve converges</div><div> </div><div>We’re looking for a Physical Design Timing Expert to join the growing Technology Methodology &amp; Execution team, that is responsible for developing both Technology Methodologies &amp; Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.   </div><h3>What will your job look like:</h3><ul><li>Leading Subsystem/IP Timing activities for complex Sub FullChip with several levels of hierarchies.</li><li>Timing  rollup , analysis &amp; of blocks &amp; sub system levels &amp; timing signoff on Function &amp; Scan models on Sub FC /IP level.</li><li>Define timing signoff methodologies, corners, derates margins and improve QoR &amp; convergence.</li><li>Involved in the chip design &amp; architecture definition for both functional &amp;  DFT domain.</li><li>Serve as the technical STA lead while mentoring and guiding team members.</li></ul><h3>All you need is:</h3><ul><li>BSc/MSc in Electrical Engineering/Computer Science.</li><li>8+ years of experience in VLSI backend (RTL2GDS).</li><li>5+ years of experience in IP or Full Chip or IP level STA on complex SoCs.</li><li>Expert  knowledge in timing closure &amp; signoff methodologies. </li><li>Experience  with DFT architecture, Async timing concepts &amp; verification.</li><li>Experience  in technically leading complex backend activities, preferably of complete SoCs.</li><li>Expert  knowledge of the entire backend design flow from RTL to TO (Synthesis, FP,  PnR, CTS, STA, LP, EM/IR, Chip Integration).</li><li>Team player with excellent communication skills, customer orientation, and a “can-do” attitude.</li></ul>

Mobileye

Physical Design Sub Full Chip / IP Timing Lead

Mobileye

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