<h1><b>Job Details:</b></h1><p></p><p></p><h2>Job Description: </h2>Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification.<p></p><p></p><h2><b>Qualifications:</b></h2><p>Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.<br /><br />Minimum Qualifications:</p><ul><li>Graduate Computer Science/Electronics/Mathematics</li><li>Minimum 7 years of experience in verification domain, e (Specman) and/or SV languages</li><li>Experience with industry-standard EDA tools and simulation environments</li><li>High programming and debugging skills</li><li>Knowledge of Digital Integrated Circuits</li><li>Knowledge of Hardware Description Languages (VHDL/Verilog) desired</li><li>Knowledge of scripting tools and languages (Perl, python)</li><li>Knowledge of development tools (DVT, versioning tools)</li><li>Proficiency with OOP (C++, Java)</li><li>Good communication skills and strong interpersonal skills</li></ul><p><br />Preferred Qualifications:</p><ul><li>Knowledge of AI/ML integration in verification workflows</li><li>Familiarity with Formal methodology and tools</li><li>Debugging RTL failures</li><li>Open mind and an unparalleled ability to learn a new design and new verification methodologies.</li></ul><p><br />Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.</p><p></p><p>          </p><p></p><p></p><h2>Job Type:</h2>Experienced Hire<p></p><p></p><h2>Shift:</h2>Shift 1 (Romania)<p></p><p></p><h2>Primary Location: </h2>Virtual Romania<p></p><p></p><h2>Additional Locations:</h2><p></p><p></p><p></p><p></p><h2>Business group:</h2>The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.<p></p><p></p><h2>Posting Statement:</h2>All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.<h2></h2><h2>Position of Trust</h2>N/A<p></p><p><b>Work Model for this Role</b></p>This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need.  However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.