<h1>Job Details:</h1><h2>Job Description: </h2>The DFT Senior Principal Engineer  is responsible for developing logic design, RTL coding, simulation, and delivering comprehensive DFT solutions to support manufacturing and high-volume production. This includes timing closure, test content generation, and delivery for various DFx methodologies such as SCAN, MBIST, and BSCAN.Key Responsibilities:<ul><li>RTL Design &amp; Simulation<ul><li>Develop logic design and RTL code for DFT features including SCAN, MBIST, BSCAN, TAP, processor monitors, and in-system test/BIST.</li><li>Perform simulation and timing closure to ensure robust and efficient DFT implementation.</li></ul></li><li>Architecture &amp; Microarchitecture Collaboration<ul><li>Participate in defining architecture and microarchitecture for blocks and SoCs under DFT scope.</li><li>Collaborate with cross-functional teams to align DFT features with overall design goals.</li></ul></li><li>Manufacturing Test Enablement<ul><li>Develop high-volume manufacturing (HVM) test content for rapid bring-up and production ramp on automatic test equipment (ATE).</li><li>Generate and deliver test content to manufacturing, ensuring readiness for production.</li></ul></li><li>Integration &amp; Optimization<ul><li>Integrate DFT logic into functional IP and SoC designs, supporting SoC teams to ensure high-quality integration.</li><li>Optimize logic to meet power, performance, area (PPA), timing, test coverage, DPM, and test time/vector memory reduction goals.</li></ul></li><li>Verification &amp; Debug<ul><li>Review and drive verification plans to ensure DFT features meet architectural specifications.</li><li>Resolve RTL test failures and implement corrective actions to ensure feature correctness.</li></ul></li><li>Post-Silicon &amp; Continuous Improvement<ul><li>Collaborate with post-silicon and manufacturing teams to validate DFT features on silicon.</li><li>Support debug efforts and document learnings to drive continuous improvement in design and validation processes.</li></ul></li><li>Quality &amp; Coverage<ul><li>Drive high structural and IP-specific test coverage to meet product quality and DPM objectives.</li></ul></li></ul><h2>Qualifications:</h2>Minimum Qualifications Bachelor’s degree in Electrical Engineering, Computer Science, or a related field with 12+ years of industry experience, Technical Expertise:<ul><li>8+ years of hands-on experience in Design-for-Test (DFT) methodologies</li><li>Proven experience in Array Test, including Memory Built-In Self-Test (MBIST)</li></ul>Preferred Qualifications:<ul><li>Expertise in Tessent DFT tools for scan insertion, MBIST, and test pattern generation</li><li>Strong proficiency in PrimeTime, particularly in developing and managing DFT-specific timing constraints</li></ul>          <h2>Job Type:</h2>Experienced Hire<h2>Shift:</h2>Shift 1 (United States of America)<h2>Primary Location: </h2>Virtual US<h2>Additional Locations:</h2><h2>Business group:</h2>The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.<h2>Posting Statement:</h2>All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.<h2></h2><h2>Position of Trust</h2>This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.Benefits:We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:<a href="https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003" target="_blank">https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003</a>  Annual Salary Range for jobs which could be performed in the US:  $247,810.00-349,850.00 USD  The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.  Work Model for this RoleThis role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 11/25/2025